The background description provided herein is for the purpose of generally presenting the context of the disclosure. Work of the presently named inventors, to the extent it is described in this background section, as well as aspects of the description that may not otherwise qualify as prior art at the time of filing, are neither expressly nor impliedly admitted as prior art against the present disclosure. Unless otherwise indicated herein, the approaches described in this section are not prior art to the claims in the present disclosure and are not admitted to be prior art by inclusion in this section.
Information stored in a memory, such as a dynamic random access memory (DRAM) may be read by a receiver circuit in a memory controller hub (MCH) by comparing a data signal from the memory to a reference voltage. The data signal may generally have a first voltage level to represent a first logical value (e.g., a logic 0), and a second voltage level to represent a second logical value (e.g., a logic 1). The reference voltage is typically set at the average DC voltage level of the data signal, between the first and second voltage levels. However, the average DC voltage level can vary for memory of different characteristics (e.g., memory that follows a different memory protocol, different memory ranks of a dual inline memory module (DIMM), different configurations of the DIMM and/or differences between memory of different manufacturers).